technical data IW4502B strobed hex inverter/buffer high-voltage silicon-gate cmos ordering information IW4502Bn plastic IW4502Bd soic t a = -55 to 125 c for all packages the IW4502B consists of six inverter/buffers with 3-state outputs. a logic ?1? on the output enable input produces a high impedance state in all six outputs. this feature permits common busing of the outputs, thus simplifying system design. a logic ?1? on the direction input switches all six outputs to logic ?0? if the output enable input is a logic ?0?. ? operating voltage range: 3.0 to 18 v ? maximum input current of 1 a at 18 v over full package-temperature range; 100 na at 18 v and 25 c ? noise margin (over full p ackage temperature range): 1.0 v min @ 5.0 v supply 2.0 v min @ 10.0 v supply 2.5 v min @ 15.0 v supply pin assignment logic diagram pin 16=v cc pin 8= gnd function table inputs output output enable direction a y l l l h l l h l l h x l h x x z z = high impedance x = don?t care rev. 00
IW4502B rev. 00 maximum ratings * symbol parameter value unit v cc dc supply voltage (referenced to gnd) -0.5 to +20 v v in dc input voltage (referenced to gnd) -0.5 to v cc +0.5 v v out dc output voltage (referenced to gnd) -0.5 to v cc +0.5 v i in dc input current, per pin 10 ma p d power dissipation in still air, plastic dip+ soic package+ 750 500 mw p d power dissipation per output transistor 100 mw tstg storage temperature -65 to +150 c t l lead temperature, 1 mm from case for 10 seconds (plastic dip or soic package) 260 c * maximum ratings are those values beyond which damage to the device may occur. functional operation should be restricted to the reco mmended operating conditions. +derating - plastic dip: - 10 mw/ c from 65 to 125 c soic package: : - 7 mw/ c from 65 to 125 c recommended operating conditions symbol parameter min max unit v cc dc supply voltage (referenced to gnd) 3.0 18 v v in , v out dc input voltage, output voltage (referenced to gnd) 0 v cc v t a operating temperature, all package types -55 +125 c this device contains protection circuitry to guard agains t damage due to high static voltages or electric fields. however, precautions must be taken to avoid applications of any voltage highe r than maximum rated voltages to this high-impedance circuit. for proper operation, v in and v out should be constrained to the range gnd (v in or v out ) v cc . unused inputs must always be tied to an appropriate logic voltage level (e.g., either gnd or v cc ). unused outputs must be left open.
IW4502B rev. 00 dc electrical characteristics (voltages referenced to gnd) v cc guaranteed limit symbol parameter test conditions v -55 c 25 c 125 c unit v ih minimum high-level input voltage v out =0.5 v v out =1 v v out =1.5 5.0 10 15 3.5 7 11 3.5 7 11 3.5 7 11 v v il maximum low - level input voltage v out = v cc - 0.5v v out = v cc - 1.0 v v out = v cc - 1.5v 5.0 10 15 1.5 3 4 1.5 3 4 1.5 3 4 v v oh minimum high-level output voltage v in =gnd 5.0 10 15 4.95 9.95 14.95 4.95 9.95 14.95 4.95 9.95 14.95 v v ol maximum low-level output voltage v in = v cc 5.0 10 15 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 v i in maximum input leakage current v in = gnd or v cc 18 0.1 0.1 1.0 a i cc maximum quiescent supply current (per package) v in = gnd or v cc 5.0 10 15 20 1 2 4 20 1 2 4 20 30 60 120 600 a i ol minimum output low (sink) current v in = gnd or v cc u ol =0.4 v u ol =0.5 v u ol =1.5 v 5.0 10 15 3.84 9.6 25.2 3.06 7.8 20.4 2.16 5.4 14.4 ma i oh minimum output high (source) current v in = gnd or v cc u oh =2.5 v u oh =4.6 v u oh =9.5 v u oh =13.5 v 5.0 5.0 10 15 -2 -0.64 -1.6 -4.2 -1.6 -0.51 -1.3 -3.4 -1.15 -0.36 -0.9 -2.4 ma i oz maximum tree-state leakage current output in high-impedance state v in = gnd or v cc v out = gnd or v cc 18 0.4 0.4 12 a
IW4502B rev. 00 ac electrical characteristics (c l =50pf, r l =200k unless otherwise specified, input t r =t f =20 ns) v cc guaranteed limit symbol parameter v -55 c 25 c 125 c unit t phl maximum propagation delay, input a or direction to output y (figure 1) 5.0 10 15 270 120 80 270 120 80 540 240 160 ns t plh maximum propagation delay, input a or direction to output y (figure 1) 5.0 10 15 380 180 130 380 180 130 760 360 260 ns t phz maximum propagation delay, output enable to output y (figure 2) r l = 1 k 5.0 10 15 120 80 60 120 80 60 240 160 120 ns t pzh maximum propagation delay, output enable to output y (figure 2) r l = 1 k 5.0 10 15 220 100 80 220 100 80 440 200 160 ns t plz maximum propagation delay, output enable to output y (figure 2) r l = 1 k 5.0 10 15 250 130 110 250 130 110 500 260 220 ns t pzl maximum propagation delay, output enable to output y (figure 2) r l = 1 k 5.0 10 15 250 110 80 250 110 80 500 220 160 ns t tlh maximum output transition time, any output (figure 1) 5.0 10 15 200 100 80 200 100 80 400 200 160 ns t thl maximum output transition time, any output (figure 1) 5.0 10 15 120 60 40 120 60 40 240 120 80 ns c in maximum input capacitance - 7.5 pf c out maximum tree-state output capacitance (output in high-impedance state) - 15 pf
IW4502B figure 1. switching waveforms figure 2. switching waveforms expanded logic diagram (1/6 of the device) rev. 00
IW4502B n suffix plastic dip (ms - 001bb) symbol min max a 18.67 19.69 b 6.1 7.11 c 5.33 d 0.36 0.56 f 1.14 1.78 g h j 0 10 k 2.92 3.81 notes: l 7.62 8.26 1. dimensions ?a?, ?b? do not include mold flash or protrusions. m 0.2 0.36 maximum mold flas h or protrus ions 0.25 mm (0.010) per s ide. n 0.38 d suffix soic (ms - 012ac) symbol min max a 9.8 10 b 3.8 4 c 1.35 1.75 d 0.33 0.51 f 0.4 1.27 g h j 0 8 notes: k 0.1 0.25 1. dimensions a and b do not include mold flash or protrusion. m 0.19 0.25 2. maximum mold flas h or protrus ion 0.15 mm (0.006) per s ide p 5.8 6.2 for a; for b ? 0.25 mm (0.010) per s ide. r 0.25 0.5 5.72 2.54 7.62 1.27 dimens ion, mm dimens ion, mm a b h c k c m j f m p g d r x 45 seating plane 0.25 (0.010) m t -t- 1 16 8 9 l h m j a b f g d seating plane n k 0.25 (0.010) m t -t- c 1 16 8 9 rev. 00
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